Semiconductor memory device

ABSTRACT

A semiconductor memory device comprising a memory cell array consisting of a plurality of cell transistors, and additional transistors connected between bit lines and a reference potential point for suppressing the lowering of the potential of a bit line when said semiconductor memory device is changed from a non-operative state to an operative state.

TECHNICAL FIELD

The present invention relates to a semiconductor memory device and, moreparticularly, an integrated circuit semiconductor memory device, such asan erasable, programmable read only memory (EPROM) device of thefloating gate avalanche injection metal oxide semiconductor (FAMOS)type.

The circuit of a prior art EPROM device of the double gate FAMOS type isillustrated in FIG. 1. Drain electrodes of double gate FAMOS transistorsT₁₁, T₁₂ . . . T_(1n) ; T₂₁, T₂₂ . . . T_(2n) ; . . . T_(m1), T_(m2) . .. T_(mn) are connected to bit lines B₁, B₂ . . . B_(n). Gate electrodesof the double gate FAMOS transistors are connected to word lines W₁, W₂. . . W_(m) which are controlled by decoders DW₁ DW₂ . . . DW_(m).Source electrodes of the double gate FAMOS transistors are connected toa point of reference potential such as ground. Thus, each of the doublegate FAMOS transistors constitutes a one-bit cell of the memory devicehaving a memorizing capacity of m x n bits. Load circuits 11, 12 . . .1n are connected between the bit lines B₁, B₂ . . . B_(n) and a powersource V.sub. cc. Information in the form of "1" or "0" in the memorydevice of FIG. 1 can be read out in accordance with the ON state or theOFF state of each of n double gate FAMOS transistors connected to a wordline selected from the m word lines.

Since the signal PD applied to the decoders are LOW during thenon-operative period, in the memory device of FIG. 1, the potentials ofthe outputs of the decoders connected to the word lines are switched toHIGH and, hence, the potentials of all of the word lines are switched toHIGH during the non-operative period, in order to reduce powerconsumption.

The changes of the potentials of the word lines w₁ and w₂ through w_(m)and the bit line B₁ are illustrated in FIG. 2. It is assumed that theword line w₁ is selected during the period t₁ to t₂ and the abovedescribed reduction of power consumption is effected during the periodt₂ to t₃. The potential of the bit line B₁ is HIGH during the period t₁to t₂ if the cell transistor selected by the potential of the word linew₁ is in the OFF state. During the period t₂ to t₃, in which thereduction of power consumption is effected, the potentials of thenon-selected word lines w₂ through w_(m) are made HIGH, and thepotential of the bit line B₁ is made LOW, if at least one cell connectedto the bit line becomes ON state. The memory device is again renderedoperative after the power reduction period t₂ to t₃ is over. Thepotential of selected word line w₁ remains HIGH and the potentials ofnon-selected word lines w₂ through w_(m) fall to a LOW level.

However, the potential of the bit line B₁, which has been kept LOWduring the period t₂ through t₃, cannot directly switch to a HIGH level.If only a few number of cells in ON state are connected to the bit line,after t₃, the potential of the bit line B₁ falls to a much lower levelduring the period t₃ to t₄ '. This is because capacitance couplingexists due to parasitic capacitance between the drain electrode of thecell transistor connected to the bit line and the gate electrodeconnected to the word line of the cell transistor; if a greater numberof cells in ON state are connected to the bit line, the potential of thebit line is clamped by the reference potential through such cells in theON state and accordingly does not fall below the reference potential;accordingly, the potential of the bit line after t₃ depends upon thenumber of cells in the ON state connected to the bit line, and;accordingly, the fewer the number of cells in the ON state, the lowerthe potential of the bit line. Thus, a longer time is required tocomplete the charging of the bit line so as to attain the HIGH potentialof the bit line, with the result that the speed of operation of thememory device is reduced. This reduction of the operation speed isdisadvantageous in a semiconductor memory device.

The general characteristics of the prior art EPROM device are disclosedin, for example, the thesis "16 K Bit Ultraviolet Ray IrradiationErasure Type EPROM", by Kanichi Harima et al, Mitsubishi Denki Giho,Volume 53, No. 7, pages 487 to 490, 1979.

The present invention has been proposed in order to prevent the abovedescribed disadvantages in the prior art semiconductor memory device.

DISCLOSURE OF THE INVENTION

It is the main object of the present invention to provide asemiconductor memory device, in which the reduction of the powerconsumption is effected by switching the potentials of all of the wordlines to HIGH during the non-operative period, without reducing theoperational speed of the semiconductor memory device.

In accordance with the present invention a semiconductor memory deviceis provided which comprises a plurality of word lines, a plurality ofbit lines and a plurality of cell transistors, each of which isconnected between one of the bit lines and a point of referencepotential, the semiconductor memory device is characterized in thatadditional transistors are connected between the bit lines and the pointof reference potential, whereby the suppression of the lowering of thepotential of a bit line is effected by the additional transistors whenthe semiconductor memory device changes from the non-operative stateinto the operative state.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates the circuit of the prior art EPROM device of thedouble gate FAMOS type;

FIG. 2 illustrates the changes of the potentials of a word lines and thebit line of the device of FIG. 1;

FIG. 3 illustrates a circuit of the semiconductor memory device inaccordance with an embodiment of the present invention;

FIG. 4 illustrates, as an example, the details of the load circuit usedin the device of FIG. 3, and;

FIG. 5 illustrates the changes of the potentials of the word lines andthe bit line of the device of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The semiconductor memory device in accordance with an embodiment of thepresent invention is illustrated in FIG. 3. In the device of FIG. 3, anadditional array of transistors TX₁, TX₂ . . . TX_(n) for suppressingthe change of the potential of the bit lines is inserted between the bitlines and ground. The conductance of each of the added transistors TX₁,TX₂ . . . TX_(n) is approximately one tenth of the total conductance ofall of the cell transistors which are connected to a bit line and turnedON. Except for the addition of this array of transistors TX₁, TX₂ . . .TX_(n), a word line WX and a decoder DWX for the additional array oftransistors, the device of FIG. 3 is the same as the device of FIG. 1.The potential of the word line WX does not become HIGH except for thenon-operative period. Such a prevention for being at HIGH potential isachieved by the application of the same address signals a_(o) and a_(o)to the NOR gate portion of the decoder DWX, as illustrated in FIG. 3.The load circuits 11, 12 . . . 1n are connected between the bit linesB₁, B₂ . . . B_(n) and the power source V_(cc) as in the device ofFIG. 1. An example of the load circuit 11 is illustrated in FIG. 4. Theload circuit 11 of FIG. 4 comprises a transistor 111 for selecting thebit line B₁ which receives a signal from a bit line selecting decoder21, and a circuit 112 for amplifying the information of the bit line B₁which produces an output signal to an output circuit 31.

The operation of the device of FIG. 3 will be described hereinafter withreference to FIG. 5, which illustrates the changes of the potentials ofthe word lines w₁ through w_(m) and the bit line B₁. The assumedconditions of the device of FIG. 3 are the same as describedhereinbefore with reference to FIG. 2.

During the period t₁ through t₃, the changes of the potentials of theword lines w₁ through w_(m) and the bit line B₁ are the same as in thedevice of FIG. 1. The potential of the added word line w_(x) is switchedto HIGH during the period t₂ through t₃, as are the potentials of theword lines w₂ through w_(m). After the period t₂ through t₃, thepotential of the added word line w_(x) is caused to be LOW approximatelysimultaneously with the fall of the potentials of the word lines w₂through w_(m). Thus, during the period t₃ through t₄, the bit lines B₁,B₂ . . . B_(n) are supplied with currents through the added transistorsTX₁, TX₂ . . . TX_(n), and accordingly, the potentials of the bit linesB₁ B₂ . . . B_(n) are unfailingly maintained equal to the level L.Accordingly, after the charging of the bit line B₁ starts at t₄ throughthe load circuit 11, the potential of the bit line B₁ reaches a HIGHlevel at t₅, which is earlier than t₅ ' in FIG. 2. For example, in thecase where only a few number of cells in the ON state are connected tothe bit line B₁, if the period t₃ through t₄ ' of FIG. 2 isapproximately 300 ns, the period t₃ through t₄ of FIG. 5 isapproximately 100 ns, so that the time t₅ is 200 ns earlier than thetime t₅ '. Thus, the speed of charging of the bit line B₁ is increasedand, accordingly, the speed of operation of the device of FIG. 3 isincreased compared with that of the device of FIG. 1, which are thedesired results of subject invention.

Although a preferred embodiment of the present invention has beendescribed hereinbefore, various modifications of the structure of thedevice are possible. For example, the type of transistors used in thedevice of FIG. 3 is not limited to FAMOS, and other types oftransistors, such as ordinary MOS transistors or bipolar transistors,may be used. Also, the type of memory devices used in the device of FIG.3 is not limited to EPROM, and ordinary ROMs may be used.

I claim:
 1. A semiconductor memory device comprising a plurality of wordlines, a plurality of bit lines and a plurality of cell transistors,each of which is connected between one of said bit lines and a point ofthe reference potential, characterized in that additional transistorsare connected between said bit lines and said point of referencepotential, whereby suppression of the lowering of the potential of a bitline is effected by said additional transistors when said semiconductormemory device changes from the non-operative state into the operativestate.
 2. A semiconductor memory device comprising:a referencepotential; a plurality of word lines; a plurality of bit lines; aplurality of cell transistors, each of which is connected between one ofsaid bit lines and said reference potential; means for suppressing thelowering of the potential of a bit line when the semiconductor memorydevice changes from a non-operative state into an operative state; saidmeans including a plurality of additional transistors connected betweensaid bit lines and said reference potential.
 3. The semiconductor memorydevice of claim 2, wherein said additional transistors are of the MOStype.
 4. A semiconductor memory device as set forth in claim 2, whereinsaid additional transistors are of the FAMOS type.